The present invention relates to integrated circuits, and more particularly, to an isolated gate field effect transistor (MOSFET) with a drain extension.
A MOS transistor with a drain extension allows the use of a drain voltage greater than that used for conventional MOS transistors, without damaging the gate oxide. Currently, in order to obtain such transistors, the implantation of the drain region is moved away from the gate by a photolithography step.
Moreover, to produce the drain extension zone, which has a length greater than the source extension zone, a specific implantation is carried out with lower doping than that used to produce the source and drain extensions of the conventional MOS transistors. This makes it possible to decrease the electrical field near the gate oxide.
The major drawback of the current approaches lies in the fact that the implantation of the drain region is not self-aligned with the gate, which causes an appreciable dispersion in the electrical characteristics, especially of the series resistors This is due to the alignment errors of the photolithography masks respectively used for etching the gate and for the implantation away from the drain region.
In view of the foregoing background, an object of the present invention is to provide a MOS transistor with a drain extension whose implantation of the drain region is self-aligned with the gate, and which consequently does not have dispersion of the electrical parameters described above.
This and other objects, advantages and features in accordance with the present invention are provided by a method of fabricating a MOS transistor with a drain extension comprising producing in the substrate an implanted drain region located at a distance from the gate which is greater than the distance separating the gate from the implanted source region. The method further comprises producing a drain extension zone in the substrate between the drain region and the gate.
According to a general characteristic of the invention, the method may comprise a preliminary step in which the gate of the transistor and a sacrificial block are produced on the upper surface of the substrate using a single photolithographic mask and the same gate material. The sacrificial block is separated from the gate by a distance equal to the desired length for the drain extension
Moreover, the production of the drain extension may comprise a specific implantation of dopants in the substrate between the gate and the sacrificial block. The production of the implanted drain region may comprise an implantation of dopants in the substrate zone located under the sacrificial block, after the sacrificial block has been removed. Thus, by using a single photolithographic mask to define the gate and the sacrificial block, and consequently the position of the implantation of the drain region, a drain region is obtained which is self-aligned with the gate. The drain extension region is also self-aligned with the gate.
More specifically, according to one embodiment of the invention, after the specific implantation of the drain extension, the space between the gate and the sacrificial block is filled with an isolating material to form an isolating block. The sacrificial block is removed for leaving the isolating block next to the gate and having a substantially vertical abrupt uncovered sidewall. The drain implantation is then carried out in the substrate on the same side as the uncovered sidewall of the isolating block.
In this case, the self-alignment of the implantation of the drain region results from the self-alignment of the isolating block with respect to the gate. The removal of the sacrificial block comprises, for example, the formation of a block of resin covering the gate and leaving the sacrificial block uncovered, and etching of the gate material of the sacrificial block.
According to a first variation of the invention, the formation of the isolating block may comprise deposition of an isolating layer on the structure obtained at the end of the preliminary step, chemical-mechanical polishing of the isolating layer and etching of the isolating layer on each side of the assembly formed by the gate, the sacrificial block and the isolating material placed between the gate and the sacrificial block. The isolating layer advantageously comprises a silicon nitride sublayer covered with a silicon oxide layer, such as TEOS, for example. Moreover, the chemical-mechanical polishing stops on the silicon nitride sublayer.
According to one embodiment of the invention, the method moreover comprises, after producing the implanted drain region, an additional step in which lateral isolating regions (spacers) are formed. These regions are respectively leaning against the abrupt uncovered sidewall of the isolating block and against the uncovered sidewall of the gate. These lateral isolating regions have, conventionally, a curved outer edge in contrast with the isolating block which has abrupt and substantially vertical outer edges.
According to another variation of the invention, which does not require chemical-mechanical polishing, the method comprises, after the preliminary step, a step of forming lateral isolating regions (spacers) comprising a conformal deposition on the structure obtained at the end of the preliminary step. This comprises an isolating layer having a thickness chosen depending on the width of the base desired for the lateral isolating regions. The method may further comprise an anisotropic etching of the isolating layer, so as to form lateral isolating regions leaning respectively against the gate sidewall furthest from the sacrificial block, and against the sacrificial block sidewall furthest from the gate.
Moreover, to fill the space between the gate and the sacrificial block during the conformal deposition of the isolating layer, thus forming the isolating block, the distance separating the gate and the sacrificial block is at the most equal to twice the thickness of the isolating layer deposited.
A variation may be integrated into conventional MOS transistor fabrication technology, especially with regards to producing spacers for the various transistors To be able to use the conventional method of spacer formation, the distance separating the gate and the sacrificial block must be at least twice the thickness of the isolating layer deposited, without which the space between the gate and the sacrificial block will not be filled correctly. The isolating layer forming the spacers and the isolating block advantageously comprises a silicon oxide sublayer, such as TEOS, for example, covered with a silicon nitride layer.
Another aspect of the invention is directed to a MOS transistor with a drain extension. The MOS transistor comprises an isolating block resting on the upper surface of a semiconductor substrate. This isolating block has a first sidewall next to the gate of the transistor, and a second abrupt sidewall substantially vertical and substantially parallel to the first sidewall. Moreover, the transistor comprises a drain extension zone in the substrate under the isolating block, and a drain region in contact with the drain extension zone and in a zone of the substrate located outside the isolating block.
According to one embodiment of the invention, the transistor comprises lateral isolating regions (spacers) leaning respectively against the second abrupt sidewall of the isolating block, and against the gate sidewall away from the one which is right next to the isolating block. These lateral isolating regions may have a curved outer edge. Advantageously, the isolating block comprises a silicon nitride sublayer covered with a silicon oxide layer, such as TEOS, for example.
According to another variation, the transistor comprises a lateral isolating region (spacer) leaning against the gate sidewall away from the one which is right next to the isolating block, and another lateral isolating region (spacer) located facing and at a distance from the second abrupt sidewall of the isolating block. The two lateral isolating regions may have curved outer edges. Moreover, the drain region in contact with the drain extension zone lies in a zone of the substrate located between the isolating block and this other lateral isolating region (spacer). Advantageously then, the isolating block comprises a silicon oxide sublayer covered with a silicon nitride layer.
Regardless of the embodiment, the lateral isolating regions (spacers) comprise, for example, a silicon oxide sublayer covered with a silicon nitride layer. The subject of the invention is also directed to an integrated circuit comprising at least one MOS transistor with a drain extension as defined above.